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rev 1.11 7/31/00 characteristics subject to change without notice. 1 of 15 www.xicor.com 128k x84129 mps eeprom ?ort saver eeprom features up to 10mhz data transfer rate at 5v operator 25ns read access time direct interface to microprocessors and micro- controllers eliminates i/o port requirements no interface glue logic required eliminates need for parallel to serial converters low power cmos 2.5v?.5v version standby current less than 1? active current less than 1ma byte or page write capable 32-byte page write mode typical nonvolatile write cycle time: 2ms high reliability 100,000 endurance cycles guaranteed data retention: 100 years small packages options 8-lead xbga package 14-lead soic package 28-lead tssop package description the ?ort saver memories need no serial ports or special hardware and connect to the processor mem- ory bus. replacing bytewide data memory, the ?ort saver uses bytewide memory control functions, takes a fraction of the board space and consumes much less power. replacing serial memories, the ?ort saver provides all the serial bene?s, such as low cost, low power, low voltage, and small package size, while releasing i/os for more important uses. the ?ort saver memory outputs data within 25ns of an active read signal. this is less than the read access time of most hosts and provides ?o-wait-state opera- tion. this prevents bottlenecks on the bus. with rates to 10mhz, the ?ort saver supplies data faster than required by most host read cycle speci?ations. this eliminates the need for software nops. the ?ort saver memories communicate over one line of the data bus using a sequence of standard bus read and write operations. this ?it serial interface allows the ?ort saver to work well in 8-bit, 16-bit, 32-bit, and 64-bit systems. a write protect (wp ) pin prevents inadvertent writes to the memory. xicor eeproms are designed and tested for applica- tions requiring extended endurance. inherent data retention is greater than 100 years. block diagram ce i/o h.v. generation timing & control eeprom command decode and control logic x dec y decode data register wp oe we array 16k x 8 p0/cs p1/clk p2/di p3/do system connection internal block diagram ? ? ports saved dsp asic a 15 a 0 d 7 d 0 oe we mps risc a pplication n ote a v a i l a b l e an95 ?an103 ?an107
x84129 characteristics subject to change without notice. 2 of 15 rev 1.11 7/31/00 www.xicor.com pin configurations 5 6 7 14-lead soic ce i/o nc nc nc wp v ss v cc nc nc nc nc oe we 28-lead tssop wp v ss nc nc nc oe we nc nc i/o ce nc v cc nc nc ce ce nc nc nc nc nc nc x84129 nc nc 8-lead xbga: top view nc we oe v ss wp v cc i/o ce 1 2 3 4 8 7 6 5 x84129z 1 2 3 4 14 13 12 11 10 9 8 1 2 3 4 5 6 7 24 23 22 21 20 19 18 8 9 10 17 11 12 25 26 27 28 16 15 13 14 nc nc nc x84129 pin names package selection guide pin descriptions chip enable (ce ) the chip enable input must be low to enable all read/ write operations. when ce is high, the chip is dese- lected, the i/o pin is in the high impedance state, and unless a nonvolatile write operation is underway, the device is in the standby power mode. output enable (oe ) the output enable input must be low to enable the output buffer and to read data from the device on the i/ o line. write enable (we ) the write enable input must be low to write either data or command sequences to the device. data in/data out (i/o) data and command sequences are serially written to or serially read from the device through the i/o pin. write protect (wp ) when the write protect input is low, nonvolatile writes to the device are disabled. when wp is high, all func- tions, including nonvolatile writes, operate normally. if a nonvolatile write cycle is in progress, wp going low will have no effect on the cycle already underway, but will inhibit any additional nonvolatile write cycles. device operation the x84129 are serial eeproms designed to inter- face directly with most microprocessor buses. stan- dard ce , oe , and we signals control the read and write operations, and a single l/o line is used to send and receive data and commands serially. data timing data input on the l/o line is latched on the rising edge of either we or ce , whichever occurs ?st. data output on the l/o line is active whenever both oe and ce are low. care should be taken to ensure that we and oe are never both low while ce is low. pin description i/o data input/output ce chip enable input oe output enable input we write enable input wp write protect input v cc supply voltage v ss ground nc no connect 84129 8-lead xbga 14-lead soic 28-lead tssop
x84129 characteristics subject to change without notice. 3 of 15 rev 1.11 7/31/00 www.xicor.com read sequence a read sequence consists of sending a 16-bit address followed by the reading of data serially. the address is written by issuing 16 separate write cycles (we and ce low, oe high) to the part without a read cycle between the write cycles. the address is sent serially, most signi?ant bit ?st, over the i/o line. note that this sequence is fully static, with no special timing restric- tions, and the processor is free to perform other tasks on the bus whenever the device ce pin is high. once the 16 address bits are sent, a byte of data can be read on the i/o line by issuing 8 separate read cycles (oe and ce low, we high). at this point, writing a ? will terminate the read sequence and enter the low power standby state, otherwise the device will await further reads in the sequential read mode. sequential read the byte address is automatically incremented to the next higher address after each byte of data is read. the data stored in the memory at the next address can be read sequentially by continuing to issue read cycles. when the highest address in the array is reached, the address counter rolls over to address $0000 and reading may be continued inde?itely. reset sequence the reset sequence resets the device and sets an internal write enable latch. a reset sequence can be sent at any time by performing a read/write ??read operation (see figs. 1 and 2). this breaks the multiple read or write cycle sequences that are normally used to read from or write to the part. the reset sequence can be used at any time to interrupt or end a sequential read or page load. as soon as the write ? cycle is complete, the part is reset (unless a nonvolatile write cycle is in progress). the second read cycle in this sequence, and any further read cycles, will read a high on the l/o pin until a valid read sequence (which includes the address) is issued. the reset sequence must be issued at the beginning of both read and write sequences to be sure the device initiates these opera- tions properly. figure 1. read sequence ce oe we i/o (in) "0" reset when accessing: x84129 array: a15?14=0 load address read data a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 i/o (out) d7 d6 d5 d4 d3 d2 d1 d0
x84129 characteristics subject to change without notice. 4 of 15 rev 1.11 7/31/00 www.xicor.com figure 2. write sequence ce oe we i/o (in) "0" "0" "1" reset load address load data start nonvolatile write a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 i/o (out) a15 a14 a13 a12 a11 a10 a9 when accessing: x84129 array: a15?14=0 write sequence a nonvolatile write sequence consists of sending a reset sequence, a 16-bit address, up to 32 bytes of data, and then a special ?tart nonvolatile write cycle command sequence. the reset sequence is issued ?st (as described in the reset sequence section) to set an internal write enable latch. the address is written serially by issuing 16 separate write cycles (we and ce low, oe high) to the part without any read cycles between the writes. the address is sent serially, most signi?ant bit ?st, on the l/o pin. up to 32 bytes of data are written by issu- ing a multiple of 8 write cycles. again, no read cycles are allowed between writes. the nonvolatile write cycle is initiated by issuing a spe- cial read/write ??read sequence. the ?st read cycle ends the page load, then the write ? followed by a read starts the nonvolatile write cycle. the device rec- ognizes 32-byte pages. when sending data to the part, attempts to exceed the upper address of the page will result in the address counter ?rapping-around to the ?st address on the page, where data loading can continue. for this rea- son, sending more than 256 consecutive data bits will result in overwriting previous data. a nonvolatile write cycle will not start if a partial or incomplete write sequence is issued. the internal write enable latch is reset when the nonvolatile write cycle is completed and after an invalid write to prevent inad- vertent writes. note that this sequence is fully static, with no special timing restrictions. the processor is free to perform other tasks on the bus whenever the chip enable pin (ce ) is high. nonvolatile write status the status of a nonvolatile write cycle can be deter- mined at any time by simply reading the state of the l/o pin on the device. this pin is read when oe and ce are low and we is high. during a nonvolatile write cycle the l/o pin is low. when the nonvolatile write cycle is complete, the l/o pin goes high. a reset sequence can also be issued during a nonvolatile write cycle with the same result: i/o is low as long as a nonvolatile write cycle is in progress, and l/o is high when the nonvolatile write cycle is done.
x84129 characteristics subject to change without notice. 5 of 15 rev 1.11 7/31/00 www.xicor.com low power operation the device enters an idle state, which draws minimal current when: an illegal sequence is entered. the following are the more common illegal sequences: read/write/write?ny time read/write ?when writing the address or writing data. write ?when reading data read/read/write ?after data is written to device, but before entering the nv write sequence. the device powers-up; a nonvolatile write operation completes. while a sequential read is in progress, the device remains in an active state. this state draws more cur- rent than the idle state, but not as much as during a read itself. to go back to the lowest power condition, an invalid condition is created by writing a ? after the last bit of a read operation. write protection the following circuitry has been included to prevent inadvertent nonvolatile writes: the internal write enable latch is reset upon power-up. a reset sequence must be issued to set the internal write enable latch before starting a write sequence. a special ?tart nonvolatile write command sequence is required to start a nonvolatile write cycle. the internal write enable latch is reset automatically at the end of a nonvolatile write cycle. the internal write enable latch is reset and remains reset as long as the wp pin is low, which blocks all nonvolatile write cycles. the internal write enable latch resets on an invalid write operation.
x84129 characteristics subject to change without notice. 6 of 15 rev 1.11 7/31/00 www.xicor.com absolute maximum ratings temperature under bias ....................?5 c to +135 c storage temperature .........................?5 c to +150 c terminal voltage with respect to v ss .......... ?v to +7v dc output current................................................. 5ma lead temperature (soldering, 10 seconds).........300 c comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions (above those indi- cated in the operational sections of this speci?ation) is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. recommended operating conditions temperature min. max. commercial 0 c +70 c industrial ?0 c +85 c supply voltage limits x84129-2.5 2.5v to 5.5v d.c. operating characteristics (v cc = 5v 10%) (over the recommended operating conditions, unless otherwise speci?d.) note: (1) v il min. and v ih max. are for reference only and are not tested. symbol parameter limits unit test conditions min. max. i cc1 v cc supply current (read) 1 ma oe = v il , we = v ih , i/o = open, ce clocking @ 10mhz i cc2 v cc supply current (write) 2 ma i cc during nonvolatile write cycle all inputs at cmos levels i sb1 v cc standby current 1 a ce = v cc , other inputs = v cc or v ss i li input leakage current 10 ? v in = v ss to v cc i lo output leakage current 10 ? v out = v ss to v cc v ll (1) input low voltage ?.5 v cc x 0.3 v v ih (1) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 2.1ma v oh output high voltage v cc ?0.8 v i oh = ?ma
x84129 characteristics subject to change without notice. 7 of 15 rev 1.11 7/31/00 www.xicor.com d.c. operating characteristics (v cc = 2.5v to 5.5v) (over the recommended operating conditions, unless otherwise speci?d.) capacitance t a = +25 c, f = 1mhz, v cc = 5v note: (2) periodically sampled, but not 100% tested. power-up timing note: (3) time delays required from the time the v cc is stable until the speci? operation can be initiated. periodically sampled, but not 100% tested. a.c. conditions of test symbol parameter limits unit test conditions min. max. i cc1 v cc supply current (read) 500 ? oe = v il , we = v ih , i/o = open, ce clocking @ 5mhz i cc2 v cc supply current (write) 2mai cc during nonvolatile write cycle all inputs at cmos levels i sb1 v cc standby current 1 a ce = v cc , other inputs = v cc or v ss i li input leakage current 10 ? v in = v ss to v cc i lo output leakage current 10 ? v out = v ss to v cc v ll (1) input low voltage ?.5 v cc x 0.3 v v ih (1) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 1ma, v cc = 3v v oh output high voltage v cc ?0.4 v i oh = ?00 a, v cc = 3v symbol parameter max. unit test conditions c i/o (2) input/output capacitance 8 pf v i/o = 0v c in (2) input capacitance 6 pf v in = 0v symbol parameter max. unit t pur (3) power-up to read operation 2 ms t puw (3) power-up to write operation 5 ms input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 5ns input and output timing levels v cc x 0.5
x84129 characteristics subject to change without notice. 8 of 15 rev 1.11 7/31/00 www.xicor.com equivalent a.c. load circuits symbol table 5v 30pf 2.06k ? 3.03k ? output 3v 30pf 2.39k ? 4.58k ? output 2v 30pf 2.8k ? 5.6k ? output waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance
x84129 characteristics subject to change without notice. 9 of 15 rev 1.11 7/31/00 www.xicor.com a.c. characteristics (over the recommended operating conditions, unless otherwise speci?d.) read cycle limits?84129 ? note: (4) periodically sampled, but not 100% tested. t hz and t ohz are measured from the point where ce or oe goes high (whichever occurs ?st) to the time when i/o is no longer being driven into a 5pf load. ? contact factory for 10mhz x84129 availability read cycle symbol parameter v cc = 2.5v ?5.5v unit min. max. t rc read cycle time 200 ns t ce ce access time 50 ns t oe oe access time 50 ns t oel oe pulse width 60 ns t oeh oe high recovery time 60 ns t low ce low time 70 ns t high ce high time 120 ns t lz (4) ce low to output in low z 0 ns t hz (4) ce high to output in high z 0 30 ns t olz (4) oe low to output in low z 0 ns t ohz (4) oe high to output in high z 0 30 ns t oh output hold from ce or oe high 0 ns t wes we high setup time 25 ns t weh we high hold time 25 ns ce we t wes oe t high t ce t oe t olz t oh t weh high z data t ohz t hz t lz t low t rc i/o t oel t oeh
x84129 characteristics subject to change without notice. 10 of 15 rev 1.11 7/31/00 www.xicor.com write cycle limits?84129 notes: (5) t nvwc is the time from the falling edge of oe or ce (whichever occurs last) of the second read cycle in the ?tart nonvolatile write cycle sequence until the self-timed, internal nonvolatile write cycle is completed. (6) data is latched into the x84129 on the rising edge of ce or we , whichever occurs ?st. (7) periodically sampled, but not 100% tested. ce controlled write cycle symbol parameter v cc = 2.5v ?5.5v unit min. max. t nvwc (5) nonvolatile write cycle time 5 ms t wc write cycle time 200 ns t wp we pulse width 40 ns t wph we high recovery time 150 ns t cs write setup time 0 ns t ch write hold time 0 ns t cp ce pulse width 40 ns t cph ce high recovery time 150 ns t oes oe high setup time 25 ns t oeh oe high hold time 25 ns t ds (6) data setup time 20 ns t dh (6) data hold time 5 ns t wpsu (7) wp high setup 100 ns t wphd (7) wp high hold 100 ns ce oe t wph we wp i/o t oes t cph t oeh t ch t wphd high z data t ds t dh t cp t wp t wpsu t cs t wc
x84129 characteristics subject to change without notice. 11 of 15 rev 1.11 7/31/00 www.xicor.com we controlled write cycle ce oe t wph we wp i/o t oes t cph t ch t oeh t wphd high z data t ds t dh t cp t wp t wpsu t cs t wc
x84129 characteristics subject to change without notice. 12 of 15 rev 1.11 7/31/00 www.xicor.com packaging information x84129: bottom view note: all dimensions in ? (to convert into inches, 1? = 3.94 x 10 -5 inch) all dimensions are typical values 8-lead xbga package complete part number top mark xaag x84129z - 2.5 xadf x84129zi - 2.5 8-lead xbga: top view nc we oe v ss wp v cc i/o ce 1 2 3 4 8 7 6 5 .078 in. .238 in. 1200?0 500?0 1000?0 430?5 1982?0 1833?0 6046?0 6046?0 350?0 i/o ce v ss wp v cc nc we oe 180?0 180?0 350?0 pin 1 8-lead xbga
x84129 characteristics subject to change without notice. 13 of 15 rev 1.11 7/31/00 www.xicor.com packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.020 (0.51) pin 1 pin 1 index 0.050 (1.27) 0.336 (8.55) 0.345 (8.75) 0.004 (0.10) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 14-lead plastic small outline gullwing package type s note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050"typical 0.050"typical 0.030"typical 14 places footprint 0.010 (0.25) 0.020 (0.50) 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0??8 x 45
x84129 characteristics subject to change without notice. 14 of 15 rev 1.11 7/31/00 www.xicor.com packaging information note: all dimensions in inches (in parentheses in millimeters) 28-lead plastic, tssop package type v .169 (4.3) .177 (4.5) .252 (6.4) bsc .026 (.65) bsc .377 (9.60) .385 (9.80) .002 (.06) .005 (.15) .047 (1.20) .0075 (.19) .0118 (.30) see detail ? .031 (.80) .041 (1.05) 0??8 .010 (.25) .020 (.50) .030 (.75) gage plane seating plane detail a (20x) (4.16) (7.72) (1.78) (0.42) (0.65) all measurements are typical
x84129 characteristics subject to change without notice. 15 of 15 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue produ ction and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. trademark disclaimer: xicor and the xicor logo are registered trademarks of xicor, inc. autostore, direct write, block lock, serialflash, mps, and xd cp are also trademarks of xicor, inc. all others belong to their respective owners. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and addition al patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ?icor, inc. 2000 patents pending rev 1.11 7/31/00 www.xicor.com ordering information part mark convention device x84129 x x temperature range blank = commercial = 0? to +70? i = industrial = ?0? to +85? ? v cc range 2.5 = 2.5v to 5.5v packages x84129 s14 = 14-lead soic v28 = 28-lead tssop z = 8-lead xbga 8-lead xbga package complete part number top mark xaag x84129z-2.5 xadf x84129zi-2.5

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